Co - design of Fault - Tolerant Systems with Imperfect Fault Detection

In recent decades, transient faults have become a critical issue in modern electronic devices. Therefore, many fault-tolerant techniques have been proposed to increase system reliability, such as active redundancy, which can be implemented in both space and time dimensions. The main challenge of active redundancy is to introduce the minimal overhead of redundancy and to schedule the tasks. In many pervious works, perfect fault detectors are assumed to simplify the problem. However, the induced resource and time overheads of such fault detectors make them impractical to be implemented. In order to tackle the problem, an alternative approach was proposed based on imperfect fault detectors. So far, only software implementation is studied for the proposed imperfect fault detection approach. In this thesis, we take hardware-acceleration into consideration. Field-programmable gate array (FPGA) is used to accommodate tasks in hardware. In order to utilize the FPGA resources efficiently, the mapping and the selection of fault detectors for each task replica have to be carefully decided. In this work, we present two optimization approaches considering two FPGA technologies, namely, statically reconfigurable FPGA and dynamically reconfigurable FPGA respectively. Both approaches are evaluated and compared with the proposed software-only approach by extensive experiments.